sequential (109) Rugby Design (Segment and Rugby)

https://kamchihau.blogspot.com/2024/07/sequential-109.html

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Ref: https://kamchihau.blogspot.com/2024/07/sequential-109.html?m=1

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John : See the 1st picture.  There're 2 registers in the  circuit.  They are R0 and R1.

Me: Ok.

John:  The modulator send a control's signal to both R0 and R1. The end of the Load shift line of R0 doesn't link to the beginning of the Load shift line of R1.

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Me: In the case of "Load shift line", "Output availability line", a Rugby Design is more suitable cause those line is Boolean relationship. 

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John: Boolean relationship means it's either true or false. It's either 0 or 1.

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"Load shift line [either 0 or 1]", 

"Output availability line [either 0 or 1]"

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Me: Ok.

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John: See the 3rd picture.  In a workable circuit,  there must be at least 4 clock lines.  They are the Clock lines of RJ45,  Satellite's Antenna, System and internal for-loop. 

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Me: Ok.

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John : I give you an example of internal for-loop

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For (int I =0; i < 100; i++)

{

}

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