Two hackers police public hospital Hong kong 911 world trade center

https://kamchihau.blogspot.com/2022/12/httpskamchihau_24.html . . Ref: https://wodewangzhishime.blogspot.com/2022/12/i-know-everythings.html . . . . . John: The 1st picture is a simple If-Else's register.  Both the value of Ca and Ba enter the Xor gate. . If (Xor gate = true) { Cv = Bv } Me: Ok. John : Of the 2nd and 3rd Picture,  which picture is logical.  Me: The 2nd picture is logical.  Why? When the Clk line of RJ45 is at up cycle,  the Clock input of CV, CA, BV, BA are at up cycle.  John: You are wrong.  When the clock line of RJ45 is at up cycle,  the Clock input of BV, BA, CV are at Up Cycle.  But, the clock input of CA is at down cycle.  . Me: How can it be ? . John : Hackers hack the Clock line of RJ45.  Eventually,  it become,  . If (Xor gate = true) { Cv isn't equal to BV.  }

  https://kamchihau.blogspot.com/2022/12/httpskamchihau.html . Ref:  https://wodewangzhishime.blogspot.com/2022/02/httpswodewangzhishime_26.html  . . . . . John: Take a look.  . 1)  https://wodewangzhishime.blogspot.com/2022/02/httpswodewangzhishime_26.html . 2) https://wodewangzhishime.blogspot.com/2022/02/httpswodewangzhishime_80.html?m=1 . 3)  https://kamchihau.blogspot.com/2022/11/impact.html?m=1  . . Me: Ok. . John : See the 1st picture.  In fact the parallel input and output line is virtual.  . Me: The Chosen Clock line is virtual either.  . John : Yes, see the 2nd picture. Do you see the Question Mark ? . Me: Question Mark ? Yes, I do see them. . John: The Question Mark is the location where you gotta choose the Clock line,  e.g., the Clock line of the System,  the Clock line of the Satellite's Antenna,  the Clock line of RJ45,  etc.  . John : Do you see real Clock line and Virtual Clock line ? . Me: Yes...

  https://kamchihau.blogspot.com/2022/11/impact.html . Ref:  https://kamchihau.blogspot.com/2022/12/httpskamchihau_24.html . . . John : Many people misunderstand that the principle of hacking is stack overflow. However,  I tell you it's wrong.  Why ? See the 1st picture.  The clock line and output line of R1 are virtual.  . Me: That mean it's 2nd level.  . John : You gotta hack the 1st level of clock line and the 1st level of output line cause they are real and at the 1st level. Me: Fine.  . John : There's a "packaged" Wave which  is generated by Clock line of RJ45.  It's at the down cycle.  . John : Correct.  Inside this "Packaged" wave,  there're 2 carrier waves.  They are the carrier wave of R0 and the carrier wave of R1. . Me: Between the carrier wave of R0 and R1, there is a gap. . John : This Gap point block R0 from overflowing to R1. This Gap point also block R1 from Left Shifting to R0. . Me: Therefore,  ...