sequential (106) No realistic serial circuit (delay circuit)

 https://kamchihau.blogspot.com/2023/02/blog-post.html

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Ref: https://wodewangzhishime.blogspot.com/2024/02/httpswodewangzhishime.html

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John: The followings are about delay circuit. You may read them first.

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1) https://wodewangzhishime.blogspot.com/2023/12/blog-post_2.html
2) https://wodewangzhishime.blogspot.com/2023/12/sequential-94-cross.html

3) https://wodewangzhishime.blogspot.com/2023/12/blog-post_11.html

4) https://wodewangzhishime.blogspot.com/2023/12/blog-post_12.html

5) https://wodewangzhishime.blogspot.com/2023/12/blog-post_13.html

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Me: OK.

John: Now, we start. 

Me: OK.

John: Look at the pictures above. What does [3][2][1][4] mean?

Me: They mean 1,1,1,1 in binary term.

John: OK . Of the pictures above, which picture is correct?

Me: The 1st picture is correct. That mean when the left carrier wave of [2] is at up cycle, the right carrier wave of [2] is at up cycle too.

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John: You're wrong. the 2nd picture is correct too. That mean when the left carrier wave of [2] is at up cycle, the right carrier wave of [2] is at down cyle.

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Me: If the right carrier wave of [2][1][4] are at down cycle, indeed, 3, 2, 1, 4 all are input rather than just 3 is input.

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John: Correct.

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Me: Why does it happen?

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John: Take a look at this article ( https://kamchihau.blogspot.com/2024/07/sequential-109.html ).