sequential (23) no realistic serial circuit (counter)

 https://kamchihau.blogspot.com/2022/09/different-frequency.html

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Ref: https://kamchihau.blogspot.com/2022/12/tom-actually-how-many-people-in-hackers.html .

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John: This article (https://kamchihau.blogspot.com/2022/08/httpskamchihau_4.html) is about 3 state buffer. You may read that first.

Me: OK.

John: There're 3 pictures above. The 3rd picture say that the clock line is indeed the center tap. The clock line is shared by register of port A and counter. For more details, you may read this article ( https://wodewangzhishime.blogspot.com/2022/02/the-definition-of-aliens-differing-in.html ). 

Me: OK.

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John: Look at the 2nd picture. The code is that

if (Q0,Q1,Q2 = high)

{

MOV register_receive, the value of the resiter of Port A <-- this code mean that parallel output of the register of Port A is available. Where does register of Port A output to? Of course, it output to register_receive.

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John: If parallel output is available, that mean the output control of the register of Port A is "Up cycle".

Me: OK.

John: However, this article (https://wodewangzhishime.blogspot.com/2022/02/the-definition-of-aliens-differing-in.html) say that Q2 will never be "high". If Q2 will never be high, how can the output control of the register of Port A be "Up cycle"? How can register of Port A output in a parallel manner?

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Me: If the clock-input of FF3 is forever down cycle, Q2 will never be high, output control of the register of port A will never be "Up cycle", the register of port A will never output in a parallel manner .